library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity div_signed_base_4_latch_layer is
	PORT(
	clk : in STD_LOGIC; 
	start : in STD_LOGIC;
	
	numerator : in STD_LOGIC_VECTOR(31 downto 0);
	new_partial_remainder : in STD_LOGIC_VECTOR(31 downto 0);
	quotient_digit : in STD_LOGIC_VECTOR(1 downto 0);
	
	is_signed : in STD_LOGIC;
	output : out STD_LOGIC_VECTOR(63 downto 0)
	);
end div_signed_base_4_latch_layer;

architecture Behavioral of div_signed_base_4_latch_layer is
	signal latch : STD_LOGIC_VECTOR(63 downto 0);
	signal countdown : STD_LOGIC_VECTOR(4 downto 0) := "00000";
begin
	process(clk)
		
	begin
		if (clk'event and clk = '1') then
			if (start = '1' and countdown = "00000") then
				if (is_signed = '1' and numerator(31) = '1') then
					latch <= x"00000000"&STD_LOGIC_VECTOR(-signed(numerator));
				else
					latch <= x"00000000"&numerator;
				end if;
				countdown <= "10000";
			elsif (countdown /= "00000") then
				
				latch(31 downto 2) <= latch(29 downto 0);
				latch(1 downto 0) <= quotient_digit;
				latch(63 downto 32) <= new_partial_remainder;
				
				countdown <= std_logic_vector(unsigned(countdown) - 1);
				
			else
				-- hold result, do nothing
			end if;
		end if;
	end process;
	
	-- output links
	output <= latch(63 downto 0);

end Behavioral;

